The photonic core is enclosed in an aluminium box measuring 42.5 x 19.3 x 46 cm. The front panel of the box is shown in Fig. 1 a). On right-hand half of the panel, there is an optical input from the master clock (MLL), three optical inputs for the signals coming from the receivers (RX1, RX2, RX3), three optical outputs for the transmitters TXs (TX1, TX2, TX3) and one RS-232 serial input port to communicate with the internal microcontrollers. Inside, the box has three plates where photonic and electronic components are mounted. Fig. 1 b) shows the upper plate, where are hosted the three electro-optical modulators (EOMs) to convert the IF-generated radar waveforms to the optical domain before sending them through optical fibre links to the three SPs. Fig. 1 c) shows the intermediate plate, where are clearly visible the optical gate generators, i.e. a board to convert to the optical domain the electrical gates received from the serial input port. Moreover, there are the arrayed-waveguide (AWG) block, that separates the lines at different wavelengths generated by the MLL (see previous reports about the system overall architecture), the three narrow-band PDs operating the conversion of the optical signal coming from the RXs to IF in the electrical domain. After every PD, there is are three stages of amplification, whose output are to be fed into the three ADCs through coax cables. In Fig. 1 d), the lower plate is seen from the rear of the box. It hosts a power supply and the Er-doped fibre amplifiers (EDFAs) to boost the optical signal to be transmitted to the SPs and to amplify those coming from the SPs.